In general, a phase locked loop (generally, abbreviated as “PLL”) is a circuit that receives a reference frequency signal from the outside, and receives a frequency signal which is generated in the circuit and thereby output through a negative feedback loop, and controls the input two frequency signals to be output as signals having the same phase or the same frequency and also minimizing the same phase difference. The phase locked loop is widely used for a communication system or digital equipment such as clock signal generation or recovery, frequency modulation, demodulation, synthesis, and distribution, and the like.
In the case of a clock or a frequency waveform output from the phase locked loop (PLL), an inconsistent phase occurs. This phenomenon is referred to as a jitter.
Due to several reasons, the jitter occurs. For example, the jitter occurs due to noise within a circuit constituting the phase locked loop, and the jitter included in a reference frequency waveform that is received as an input of the phase locked loop is reflected as is in an output frequency waveform.
In general, the phase locked loop has a low band pass filter characteristic with respect to an input phase and thus, a high frequency component in input jitter is attenuated, which is referred to as an input jitter reduction. However, in the input jitter, a predetermined frequency component is further amplified, which is an essential phenomenon in order to maintain the negative feedback stability of the phase locked loop. The above phenomenon is referred to as a jitter peaking phenomenon. The above jitter characteristic is determined by a phase gain according to a frequency, that is, a transfer function of the phase locked loop during a process in which the input phase of the phase locked loop is transferred as an output phase.
When a bandwidth of the transfer function is small, a greater amount of input jitter may be reduced. However, on the contrary, when the bandwidth of the transfer function is larger, a low frequency jitter occurring due to noise within the circuit of the phase locked loop is further reduced. Also, in a frequency around a bandwidth of the transfer function, a gain becomes at least ‘1’ and thus, the input jitter is amplified. The smaller the gain, the smaller the jitter peaking phenomenon becomes. Therefore, it is very important to optimize the transfer function of the phase locked loop according to an application field. In particular, the above jitter characteristic is gaining importance in various application fields, such as optical communication, audio, universal serial bus (USB) communication, and the like, in which jitter is important.
In this instance, in the case of a phase locked loop of an analog scheme, the jitter characteristic is determined according to a current amount of a charge pump, a characteristic of a loop filter, a frequency gain (Hz/V) characteristic of a voltage controlled oscillator (VCO), and the like. The characteristic of the loop filter or the frequency gain characteristic of the VCO sensitively varies according to a process, voltage, temperature (PVT) change and thus, it is not easy to configure the jitter characteristic of the phase locked loop as accurately as a designer desires.
Accordingly, with recent development of a complementary metal-oxide semiconductor (CMOS) process technology, a digital phase locked loop in which the phase locked loop is configured using a digital logic circuit has been developed. A general structure of the digital phase locked loop is shown in FIG. 1.
As shown in FIG. 1, the digital phase locked loop generally includes a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO). The TDC is a block to output a digital signal having a value proportional to a phase difference between two input clocks, and performs the same function as a phase detector of an analog phase locked loop.
In the DLF, both an input signal and an output signal are digital signals and a low band pass filtering function such as a loop filter of the analog phase locked loop is configured using a digital logic.
Also, the analog phase locked loop uses a VCO with varying oscillation frequencies according to an output voltage of the loop filter. On the other hand, the digital phase locked loop uses the DCO with varying oscillation frequencies according to a digital signal that is received as an output of the DLF.
Here, as shown in FIG. 1, the digital phase locked loop also has a feedback circuit in the same structure as the analog phase locked loop. Therefore, similar to a jitter characteristic of the analog phase locked loop that may be determined by an equation of Ip (a current amount of a charge pump), Kvco (a frequency gain of the VCO), CLPF (a capacitor value of the loop filter), and RLPF (a resistance value of the loop filter), a jitter characteristic of the digital phase locked loop may also be determined as an equation based on a characteristic value of each block.
That is, in the case of the characteristic value of each block, the TDC is a resolution (ΔTDC) of the TDC that is a digital code output characteristic as compared to a phase difference between two input signals. The DLF is a z-domain transfer function, and the DCO has a characteristic value of (KDCO) in which an oscillation frequency varies when the digital code varies.
Here, the resolution (ΔTDC) of the TDC may be designed to be constant at all times in order to be insensitive to) a PVT change using a TDC of a known structure. The DLF is a circuit that includes a digital adder and a digital multiplier and thus, is not affected by the PVT change.
However, regardless of a structure of the DCO, the KDCO characteristic of the DCO is sensitive to the PVT change. In general, a complex plurality of factors work together and thereby affect the KDCO characteristic and thus, it is not easy to estimate the characteristic of KDCO.